Book

B. S. Reniwal, P. Singh, A. P. shah, & S. K. Vishvakarma, “Energy Efficient and Reliable Embedded Nanoscale Memory Design”, CRC Press, Taylor and Francis Group.,November 2023.
A P. Shah, B. S. Reniwal, Memories - Materials, Devices, Circuits and Systems, Elseveir, Guest Editor for the Special Issue 26th International Symposium on VLSI Design and Test 2022.

Selected, Peer Reviewed International Journals

Novel PVT Resilient Low-Power Dynamic XOR/XNOR Design Using Variable Threshold MOS for IoT Applications” IETE Journal of Research, Taylor & Francis, PP. 1-11, Jun-2023
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 1, pp. 445-455, March 2023.
B. Reniwal, V. Vijayvargiya, S. K. Vishvakarma and D. Dwivedi, “An Auto Calibrated Sense Amplifier for Energy Efficient SRAM with Offset Prediction Approach,” Circuits, Systems & Signal Processing (CSSP), Springer, vol. 38, no. 4, pp. 1482-1505, Apr. 2019.
B. Reniwal, P. Bhatia and S. K. Vishvakarma “Design and Investigation of Variability Aware Sense Amplifier for Low Power, High Speed SRAM, Microelectronics Journal, Elsevier, vol. 59, pp. 22-32, Jan. 2017.
B. Reniwal, V. Vijayvargiya, S. K. Vishvakarma and D. Dwivedi, “Ultra-Fast Current Mode Sense Amplifier for Small ICELL SRAM in FinFET with Improved Offset Tolerance,” Circuits, Systems & Signal Processing (CSSP), Springer, vol. 35, no. 9, pp. 3066-3085, Nov. 2015.
B. Reniwal and S. K. Vishvakarma, “A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultra Low Power SRAM,” International Journal of Electronics and Electrical Engineering, Canada, vol. 1, no. 1, pp. 1-5, Mar. 2013.
Sheikh, S. K. Vishvakarma and B. Reniwal, “An Offset Compensated Sense Amplifier Based on Charge Storage Technique for Low Power SRAM,” IEEE VLSI Circuits & Systems Letter, vol. 2, no. 2, Oct. 2016.
P. Singh, B. Reniwal, V. Vijayvargiya, V. Sharma and S. K. Vishvakarma, “Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications”, Journal of Low Power Electronics, American Scientific Publisher, vol. 13, no. 1, Mar. 2017.
V. Vijayvargiya, B. Reniwal, P. Singh and S. K. Vishvakarma, “Analog/RF Performance Attributes of an Underlap Tunnel Field Effect Transistor for Low Power Applications,” IET Electronics Letters, vol. 52, issue 7, pp. 559-560, Apr. 2016.
V. Vijayvargiya, B. Reniwal, P. Singh and S. K. Vishvakarma, “Impact of Device Engineering on Analog/RF Performances of Tunnel Field Effect Transistor,” Semiconductor Science and Technology, IOP Science, May. 2017.
P. Singh, B Reniwal, V. Vijayvargiya, and S. K. Vishvakarma, “Ultra Low Power-High Stability, Positive Feedback Controlled (PFC) 10T SRAM cell for Look up Table (LUT) Design," Integration, the VLSI Journal, Elsevier, vol. 62, pp. 1-13, Jun. 2018.
P. Singh, B. Reniwal, V. Vijayvargiya, V. Sharma and S. K. Vishvakarma, “Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications”, Circuits, Systems, and Signal Processing, Springer (Accepted)

Source

Peer/Double Blind Reviewed International Conferences

In-Memory Encryption Using XOR-Based Feistel Cipher in SRAM Array”, 57th IEEE International Symposium on Circuits and Systems (ISCAS-2024), 19-22, May 2024.
CiMComp: An Energy Efficient Compute-in-Memory based Comparator for Convolutional Neural Networks” 27th IEEE Design, Automation and Test in Europe Conference (DATE-2024), 25-27th Mar. 2024.
EASI-CiM: Event-driven asynchronous Stream-based Image Classifier with Compute-in-Memory kernels,” 25th IEEE International Symposium on Quality Electronic Design (ISQED-2024), 3-5 Apr. 2024, San Francisco. (Best Paper Award)
Enhancing Linearity and Efficiency in Multi-Bit MAC Computation for Convolution in DNNs Using SRAM Array”, 19th IEEE Asia Pacific Conference on Circuits & Systems (APCASS-2023), Nov-2023.
Approach Towards In-Memory Computing Based Hamming Code Implementation for Error Correction and Detection, 27th International Symposium on VLSI Design and Test (VDAT), 29-31 Sep-2023.
An Analog In-Memory Paradigm for Improvement in Linearity for Multi-Bit Dot-Product in SRAM Array” 27th International Symposium on VLSI Design and Test (VDAT), 29-31 Sep-2023.
Intelligent Vehicle Registration Number Plate Recognition Using Convolutional Spiking Neural Network, IEEE Circuits & System Society (CASS) Automotive RALLY, CAR-2023, Sep-2023. (Accepted Abstract)
S. Ansari, Kavitha S, S. K. Vishvakarma and B. S. Reniwal, “Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application”, IEEE 36th International Conference on VLSI Design, Jan-2023
Swetha A, A. Upadhyay and B. S. Reniwal, “Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach”, IEEE 36th International Conference on VLSI Design, Jan-2023.
Kavitha S, S. K. Vishwakarma and B. S. Reniwal, “An Approach towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array”, IEEE 26th International Symposium on VLSI Design and Test (VDAT), Jul. 2022
Kavitha S, B. S. Reniwal, and D. Dwivedi, “Compute-in-Memory SRAM Array with New Energy Efficient Reconfigurable Data Sensing Technique for Hardware Accelerators,” IEEE/ACM 59th Design Automation Conference, DAC-2022, Jul. 2022 San Francisco, USA.
Kavitha S, B. S. Reniwal and S. K. Vishvakarma,” Enabling In-Memory Computing with New Energy Efficient Assist Sense Amplifier for Boolean Computation in SRAM Array,” IEEE 35th IEEE International Conference on VLSI Design Feb-2022.
Mythai, Pregna, Kavitha S, S. K. Vishvakarma & B. S. Reniwal, “Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation,” IEEE 25th International Symposium on VLSI Design & Test, VDAT-2021.
B. Reniwal, S. K. Vishvakarma and De. Dwivedi, “Variability Aware Design of Energy Efficient SRAM in Conventional & Non-Conventional MOS Technologies: A Sense Amplifier Perspective,” 31th IEEE International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID-18), Jan. 2018.
B. Reniwal, and S. K. Vishvakarma, “A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM,” 30th IEEE International Conference on VLSI Design and 16th International Conference on Embedded Systems (VLSID-17), Jan. 2017, pp. 1-6.
B. Reniwal, S. K. Vishvakarma and D. Dwivedi, “Variability Resilient, Low Energy, Differential Current Compensation based Sense Amplifier for Robust SRAM, in Proc. of 29th IEEE International Conference on VLSI Design (VLSID-2016), Jan. 2016, pp. 1-6. (User Design Best Paper Award).
B. Reniwal, S. K. Vishvakarma and D. Dwivedi, "Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET," in Proc. ACM 25th Great Lakes Symposium on VLSI (GLSVLSI), pp. 95-98, May. 2015, Pittsburgh, USA.
P. Bhatia, B. Reniwal and S. K. Vishvakarma, “An Offset-Tolerant Self-Correcting Sense Amplifier for Robust High Speed SRAM,” in Proc. IEEE 19th International Symposium on VLSI Design and Test, (VDAT), pp. 1-6, Jun. 2015.
B. Reniwal, S. K. Vishvakarma and D. Dwivedi, “Robust Ultra Fast Data Sensing Technique for Low Power Asymmetrical SRAM with Self-Shut-Off Feature,” in Proc. IEEE Asia Pacific Conference on Post Graduate Research in Microelectronics & Electronics, (PRIME ASIA), pp. 77-82, Dec. 2013.
S. K. Vishvakarma, B. S. Reniwal, V. Sharma, C. B. Kushwah, and D. Dwivedi, “Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity", IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 1-6, Dec. 2016, India.
P. Singh, B. Reniwal, V. Vijayvargiya, V. Sharma and S. K. Vishvakarma, “A 9T SRAM for Ultra-Low Power Applications", 30th IEEE International Conference on VLSI Design and 16th International Conference on Embedded Systems, 7th-11th Jan 2017. (Accepted in PhD Forum).
A. Gupta, H. Anwer, B. Reniwal and S. K. Vishvakarma, “Analysis of Stability Issues and Power Efficiency of Symmetric and Asymmetric Low Power Nanoscale SRAM Cells”, in Proc. 2nd IEEE International Conference on Devices, Circuits and Systems - ICDCS 2014, pp. 1-6, Mar. 2014.
P. Singh, B. Reniwal and S. K. Vishvakarma, “Design of high speed DDR SDRAM Controller with Less Logic Utilization," 2nd IEEE International Conference on Devices, Circuits and Systems - ICDCS 2014, pp. 1-6, Mar. 2014.

Book Chapters

A. Upadhyay, B. S. Reniwal, S. B. Rahi, & A. Beohar, “Negative Capacitance tunnel field effect transistor impact and future scope springer nature” Springer Nature, 2024. (In Press)
Kavitha S, S. K. Vishwakarma and B. S. Reniwal, “An Approach towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array”, VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_23.
B. Reniwal and S. K. Vishvakarma, “Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM”, Book Title: VLSI Design and Test, Published by: Springer in Communication in Computers and Information Sciences (CCIS), vol. 382, pp 1-9, July 2013. DIO: 10.1007/978-3-642-42024-5_1.
Reniwal et al. “Compact Spiking Neural Network System with SiGe based Cylindrical Tunneling Transistor for Low Power Applications.” Book Title: VLSI Design and Test, Published by: Springer in Communication in Computers and Information Sciences (CCIS), pp 655-663, Aug. 2019. https://doi.org/10.1007/978-981-32-9767-8_54.

Patents

Inventors: B. Reniwal and S. K. Vishvakarma, “Offset Compensated Data Sensing Technique for Low Energy Embedded SRAM,” (Grant No. 201621034132)
Inventors: B. Reniwal, S. Chidambaram, B. Jose and D. Dwivedi, “A Novel Offset Compensated Sense Amplifier for Low Power SRAM”, Disclosure submitted for US Patent at Systems & Technology Group, IBM Bangalore India.